1. Field of the Invention
The present invention relates generally to semiconductors, and, more particularly, to anti-fuse structures.
2. Background of Invention
A fuse is a structure that is normally “on” meaning that current is flowing, but once “programmed” it is “off” meaning that current does not flow. In a fuse, programming means applying a suitable voltage so that the fuse “blows” to create an open circuit or high resistance state. An anti-fuse is a structure that is normally “off” meaning that no current flows, but once “programmed” it is “on” meaning that current does flow. In an anti-fuse, programming means applying a suitable voltage to two electrodes and forming a conductive link between them to close the circuit. In integrated circuitry memory devices, fuses and anti-fuses can be used for activating redundancy in memory chips and for programming functions and codes in logic chips. Specifically, dynamic random access memory (DRAM) and static random access memory (SRAM) may use fuses and anti-fuses for such purposes. In addition, fuses and anti-fuses can also be used to prevent decreased chip yield caused by random defects generated in the manufacturing process. Moreover, fuses and anti-fuses provide for future customization of a standardized chip design. For example, fuses and anti-fuses may provide for a variety of voltage options, packaging pin out options, or any other options desired by the manufacturer to be employed prior to the final processing. These customization possibilities make it easier to use one basic design for several different end products and help increase chip yield.
Both fuse and anti-fuse elements are essential for advanced DRAM applications, and it may be advantageous to (1) integrate the two elements into a single chip (2) that operates at normal on-chip or readily available voltages. As depicted in FIGS. 1A and 1B, existing anti-fuse structures, for example structure 100, have an anti-fuse layer 110 sandwiched between two “disconnected” conductive materials 102, 104. Fabricating the anti-fuse structure 100 requires the addition of the anti-fuse layer 110, which may increase overall fabrication complexity and costs. The anti-fuse structure 100 requires that the bulk thickness of the anti-fuse layer 110 be breached to form a conductive link 112. Because the bulk thickness of the anti-fuse layer 110 must be breached, a high programming voltage may be required to completely form the link 112 between the two conductive materials 102, 104, the thickness uniformity of the anti-fuse layer 110 directly affects the breakdown voltage and therefore the programming voltage. The thickness uniformity of the anti-fuse layer 110 may vary due to normal process (etch or deposition) uniformity. Because of typical variations in the thickness of the anti-fuse layer 110 the programming voltage may vary between anti-fuse structures on the same chip. Thus, due to thickness variations, an applied voltage may form a conductive link in thinner anti-fuse layers whereas the same applied voltage may not form a conductive link in thicker anti-fuse layers. Therefore, there is a programming yield issue with current anti-fuses which require forming a conductive link across an anti-fuse layer.
Moreover, most prior art anti-fuses require programming voltages higher than the chip supply voltage. Thus, there is a need for anti-fuses that can be programmed with, lower, readily available chip supply voltages.
Thus, there is a need for an anti-fuse device that can be easily integrated into typical process flows, operates at chip supply voltages, and may be reliably programmed.